Evaluation package
- Gate-level simulation netlists of the FPGA cores
- Self-checking SystemVerilog testbench and golden vectors
- Bit-exact Python reference model
- One-command test script for Verilator or Icarus
Bumble Bytes · FPGA and ASIC IP
RankFilter: verified median and rank-filter IP for video.
Streaming 3×3 to 7×7 median, percentile and Bayer defect-pixel-correction cores for FPGA and ASIC. A 5×5 median needs 52 comparators per pixel, against 63 for column sharing, the lowest published count we know of. Every comparator network is proved correct in Lean 4, and the cores run on Altera Cyclone V silicon.
AXI4-Stream or video timing
1, 2 or 4 pixels per clock
8 to 16-bit pixels
52 vs 63
Comparators per pixel for a 5×5 median, against column sharing (Adams 2021)
−75%
LUTs against AMD's free Vitis Vision medianBlur at 5×5, same Vivado flow at 148.5 MHz (−83 % at 7×7)
4K60
At 4 pixels per clock with 4K line buffers, every 4 px/clk core, on Artix 7, Zynq and the slowest Cyclone V grade
0 errors
In about 22 million self-test runs on Cyclone V silicon
Overview
Less logic for the same filter, with proof that it is right.
A streaming filter computes a new window every clock, and neighbouring windows overlap almost completely. RankFilter's comparator networks reuse that overlap instead of recomputing it. We found them by computer search and proved each one correct, for every input, in the Lean 4 proof assistant.
The honey-coloured stages are the comparator networks: found by search, proved in Lean 4.
Features
- Median, 25th and 75th percentile; other ranks generated on request
- 3×3, 5×5 and 7×7 windows
- Defect-pixel correction for Bayer and monochrome sensors with a run-time threshold; the monochrome core also takes a static bad-pixel map
- SEU-tolerant variants of the monochrome core recover from single-event upsets without a reset (simulated fault injection)
- 1, 2 or 4 pixels per clock
- AXI4-Stream with full back-pressure, or a smaller video-timing version (1 pixel per clock) for sensor streams that cannot stall
- Frame size set at run time; edge pixels replicated or replaced by a constant
- Pixel width is a parameter, verified at 8, 10, 12 and 16 bits
- Plain Verilog-2005 with inferred block RAM; Vivado IP Integrator packages, Quartus Platform Designer components and a VHDL package
Applications
- Hot and dead pixel correction on Bayer colour and monochrome sensors, including thermal and SWIR, from a threshold or a factory defect map
- Impulse (salt-and-pepper) noise removal
- Pre-processing for machine vision and industrial inspection
- Rank-order and grey-scale morphological filtering
- Scientific, medical and broadcast imaging
- Space imaging payloads (SEU-tolerant cores)
Supported devices
Any FPGA or ASIC flow that accepts Verilog-2005. Signed off on AMD Artix 7, Zynq 7000 and Zynq UltraScale+ (Vivado) and Altera Cyclone V (Quartus); measured on Lattice ECP5 and in the SkyWater 130 nm and ASAP7 ASIC flows.
Comparators per output pixel
Fewer comparators than published designs
Comparator count drives logic and power. RankFilter is lower than Adams' 2021 separable networks and the best single-window designs at every shipped size, apart from a tie at 3×3 and one pixel per clock.
| Window | RankFilter | Adams method | Single window | Odd-even |
|---|---|---|---|---|
| 3×3, 1 px/clk | 13 | 13† | 19 | 36 |
| 5×5, 1 px/clk | 52 | 63 | 85 | 300 |
| 5×5, 4 px/clk | 37 | 42.75† | 85 | 300 |
| 7×7, 1 px/clk | 140 | 187 | 231 | 1,176 |
| 7×7, 2 / 4 px/clk | 92 | 117† / 93.25 | 231 | 1,176 |
Adams 2021 (ACM Transactions on Graphics) is a software method that computes tiles of outputs; 187 and 93.25 are published in the paper and 63 is derived from it, and † marks our own count for his method. Single window: the smallest known networks that sort one whole window, with no sharing. Odd-even: the transposition sort that Vitis medianBlur unrolls. Only the RankFilter column is proved.
Performance
Measured size and speed
Complete filters: AXI4-Stream interface, line buffers for 2,048-pixel lines, border logic and comparator core, 8-bit pixels, 1 pixel per clock unless stated. Fmax in MHz on the slowest speed grade of each family.
| Core | Artix 7 −1, Vivado LUT / FF | Fmax | Cyclone V C8, Quartus ALM / M10K | Fmax | ECP5 −6, nextpnr LUT4 / EBR | Fmax |
|---|---|---|---|---|---|---|
| 3×3 median | 345 / 567 | 237 | 371 / 7 | 180 | 928 / 2 | 146 |
| 3×3 median, 4 px/clk | 974 / 1,526 | 237 | 939 / 8 | 180 | 2,233 / 8 | 126 |
| 5×5 median | 871 / 1,511 | 209 | 896 / 10 | 180 | 2,056 / 4 | 162 |
| 5×5 median, 4 px/clk | 2,638 / 3,766 | 225 | 2,216 / 28 | 163 | 5,184 / 15 | 154 |
| 5×5 25th percentile | 751 / 1,302 | 238 | 769 / 10 | 180 | 1,783 / 4 | 163 |
| 7×7 median | 1,969 / 3,458 | 217 | 1,941 / 20 | 167 | 4,455 / 6 | 150 |
| 7×7 median, 4 px/clk | 5,534 / 7,976 | 215 | 5,276 / 46 | 152 | 11,452 / 23 | 128 |
| Bayer DPC | 410 / 771 | 228 | 435 / 9 | 159 | 1,092 / 4 | 159 |
| Bayer DPC, 4 px/clk | 1,197 / 1,860 | 215 | 1,115 / 11 | 180 | 2,673 / 15 | 150 |
| Mono DPC with defect map | 384 / 633 | 214 | 430 / 7 | 180 | 959 / 2 | 160 |
Artix 7 xc7a35t-1: Vivado 2025.2, filter instance only, resources at 148.5 MHz. Cyclone V 5CEBA4F23C8: Quartus Prime Lite, lowest of 3 seeds; 180 MHz is the M10K block RAM's limit. ECP5 LFE5U-85F: yosys and nextpnr, lowest of 5 seeds. 1080p60 needs 148.5 MHz at 1 pixel per clock. 4K60 at 4 pixels per clock needs 4,096-pixel lines and 148.5 MHz (124.4 MHz at the active pixel rate); with 4K lines every 4 px/clk core meets 148.5 MHz on the AMD parts and on every Cyclone V seed. The datasheets list every variant, including Zynq 7000 and Zynq UltraScale+.
| Against other designs, same flow | 5×5 | 7×7 |
|---|---|---|
| AMD Vitis Vision medianBlur, Artix 7 LUTs | −75 % | −83 % |
| Same, at 4 px/clk | −64 % | Vitis does not fit |
| Strongest baseline we built, Artix 7 LUTs | −14 % | −26 % |
| Same, Cyclone V ALMs | −18 % | −22 % |
| Same, ECP5 LUT4s | −11 % | −21 % |
| Same, SkyWater 130 nm area | −16 % | −25 % |
Same harness, flow, part and line length for both designs; AMD resources at a common 148.5 MHz constraint. Vitis: Vitis_Libraries 2025.2 as shipped, the better of two HLS builds per metric, and each compared build simulated and checked for the correct median. Vitis also uses more block RAM at every size, and its 7×7 at 4 px/clk does not fit the xc7a35t. Both sign off at about the same Fmax, so speed is not the difference. The comparison brief has every size and part.
The baseline is column sharing (each column sorted once, then a selection network), built with the same generator and wrapper.
Verification
Checked at every level, from proof to silicon.
A filter that is wrong only on rare inputs can pass every demo and still fail in the field. Every claim below is backed by a repeatable script.
- Every comparator network is proved in Lean 4 to select the right rank for every input and any pixel type.
- The generated RTL is simulated on every binary window (225 for 5×5; every sorted-column state for 7×7), which by the 0-1 principle covers all pixel widths.
- SymbiYosys proves the flow control never overflows under any back-pressure and follows the AXI4-Stream rules.
- Output on photographs is byte-identical to an independent Python reference model, under random back-pressure.
- 73,577 malformed-input runs across all 24 cores (truncated frames, missing or extra start-of-frame markers): no core hung, and each returned to correct output.
- Simulated single-event upsets: none of 8,000 random flip-flop upsets needed a reset on the SEU-tolerant cores, against 4.7 % on the default core.
- On Altera Cyclone V silicon, a continuous self-test of five variants found zero mismatches in about 22 million runs at 74 to 170 MHz. Each run repeats the same two test frames under changing random back-pressure, so this is a soak test of timing and flow control.
Evaluation and licensing
Try it in your own simulator first
A simulation evaluation package is available on request. It drops into your testbench with the same module names and ports as the licensed source.
Licensed deliverables
- Verilog source for each variant: an FPGA set and an ASIC-tuned set
- Datasheets, product guides and integration notes
- Vivado IP Integrator packages, Quartus Platform Designer components and a VHDL component package
- Board self-test with expected checksum
- The Lean proof files
Custom variants
Licences per project or per company. Other window sizes, ranks, pixel widths and pixels per clock can be generated and verified to order, and integration support is available on contract.
Contract engineeringTalk to us about RankFilter
Tell us your device, resolution, frame rate and pixel width, and we'll reply with the matching variant and an evaluation package.
Documents
Datasheets
Revision 1.0, October 2026. Product guides with the full results tables are available on request.
DS-RF-01 Median and rank filters
3×3, 5×5 and 7×7 median, 25th and 75th percentile, 1 to 4 px/clk. 2 pages.
DS-RF-02 Bayer defect-pixel correction
Same-colour 3×3 correction for raw Bayer sensors, run-time threshold. 2 pages.
DS-RF-03 Monochrome defect-pixel correction
Thermal and SWIR sensors, threshold plus a static defect map. 2 pages.
DS-RF-04 SEU-tolerant defect-pixel correction
Recovers from single-event upsets without a reset. 2 pages.
CB-RF-01 RankFilter versus Vitis medianBlur
Same-flow comparison with AMD's free median filter on three AMD parts. 2 pages.
PB-RF-01 Product brief
The whole family on two pages.
Service
The same evidence for your FPGA block
The flow behind these datasheets runs on other designs too. Send one block and get implementation results on AMD, Altera and Lattice parts, a same-flow comparison with the vendor's free core, verification to coverage closure and an upset campaign, with every script to rerun it. Fixed prices, all work remote, your source kept under NDA.
Sign-off report
£2,400 fixed, about 1 week
- Vivado, Quartus and the open ECP5 flow, up to 3 parts
- Resources and Fmax over several seeds
- Comparison with the vendor's free core or your baseline
Verification sprint
£5,900 fixed, about 3 weeks
- Everything in the sign-off report
- Verilator testbench against a reference model, coverage to closure
- SymbiYosys properties on the stream and register interfaces
- Malformed-input runs
Upset campaign
£2,900 add-on, about 1 week
- Simulated upsets in flip-flops and block RAM
- Each run classed, with 95 % intervals
- The state bits that cause hangs, and checks to fix them
For one block up to about 10,000 LUTs. Larger blocks are quoted. Service sheet (PDF) · contact@bumblebytes.co.uk